AT&T 3B2 Revision 3 Internals

Introduction and Overview

This document describes the internals of the AT&T 3B2 Revision 3 systems. These systems were released in the years following the release of the Revision 1 (AT&T 3B2/300) and Revision 2 (AT&T 3B2/310 and 3B2/400) systems, and represented an evolution of the architecture. There were numerous changes to firmware, memory map, and supported hardware.

Revision 3 systems included (but were not limited to):

Some of these names are merely marketing distinctions, while others represent different processor and MMU configurations. However, they all share the same basic system architecture.

This document focuses on the CM518B system board that was used in some models of 3B2/600, 3B2/700, and 3B2/1000.

Memory Map

The memory map of the Revision 3 systems is documented in the AT&T 3B2 Computer Technical Reference Manual on page 3-11 in section 3, Functional Description.

0x00000000Read-Only Memory [EPROM]32 Bits128 KB
0x00040000Floppy Control Register8 Bits1 B
0x00042000NVRAM8 Bits2 KB
0x00044000Control and Status Register (CSR)32 Bits4 B
0x00045000Floppy DMA Page Register12 Bits
0x00046000UARTA DMA Page Register12 Bits
0x00047000UARTB DMA Page Register12 Bits
0x00048000DMA Controller (9517)8 Bits
0x00049000DUART (2681)8 Bits16 B
0x0004A000Floppy Controller (1793)8 Bits2 B
0x0004C000Fault Register 132 Bits1 W
0x0004D000Fault Register 232 Bits4 W
0x0004E000Time of Day Clock4 Bits
0x0004F000MMU (WE32106 or WE32206)
0x00200000Feature Card Slot 116 Bits2 MB (Max)
0x00400000Feature Card Slot 216 Bits2 MB (Max)
0x00600000Feature Card Slot 316 Bits2 MB (Max)
0x00800000Feature Card Slot 416 Bits2 MB (Max)
0x00A00000Feature Card Slot 516 Bits2 MB (Max)
0x00C00000Feature Card Slot 616 Bits2 MB (Max)
0x00E00000Feature Card Slot 716 Bits2 MB (Max)
0x01000000Feature Card Slot 816 Bits2 MB (Max)
0x01200000Feature Card Slot 916 Bits2 MB (Max)
0x01400000Feature Card Slot 1016 Bits2 MB (Max)
0x01600000Feature Card Slot 1116 Bits2 MB (Max)
0x01800000Feature Card Slot 1216 Bits2 MB (Max)
0x01A00000Reserved16 Bits2 MB (Max)
0x01C00000UBUS Connector16 Bits2 MB (Max)
0x02000000Main Memory32 Bits64 MB
0x06000000BUBUS Connector 116 Bits64 MB
0x0A000000BUBUS Connector 216 Bits64 MB
0x0E000000BUBUS Connector 316 Bits64 MB
0x12000000BUBUS Connector 416 Bits64 MB
0xC0F00000HW, SW Development System1 MB
0xC1000000Reserved for Diagnostics1 MB

DMA Page Registers

These are 12-bit wide registers located at 0x45000, 0x46000, and 0x47000. They are write-only registers, and are used to set up the DMA page addresses for the integral floppy drive, UART A, and UART B, respectively. They are written as half-words, and are half-word aligned.

UART A0x46002
UART B0x47002

Floppy Control Register

The Floppy Control Register at address 0x40000 is an 8-bit register used to control which floppy drive is selected, and the amount of precompensation to use when writing.

Using this register, up to four floppy drives can be addressed by a single controller.

0Floppy Drive Select 0
1Floppy Drive Select 1
2Floppy Drive Select 2
3Floppy Drive Select 3
4Precompensation Bit 0
5Precompensation Bit 1
6Precompensation Bit 2
7Force Precompensation

Fault Registers

There are two registers located at 0x4c000 and 0x4d000, respectively, called the fault registers. They are not documented in the the 3B2 Technical Reference Manual, but they are described somewhat more fully in the system header file /usr/include/sys/faultr.h.

The primary purpose is to hold information about system faults, but Fault Register 2 plays double duty. In addition to latching fault information, the bottom few bits of Fault Register 2 identify the type and number of RAM boards installed.

Fault Register 1

This 32-bit register holds the physical address of any fault in the its lower 26 bits.

Fault Register 2

This 32-bit register is a bit odd. There are actually four registers, addressed at 0x4d000, 0x4d004, 0x4d008, and 0x4d00c. The low three bits of each of these registers corresponds to the memory equipped and memory size bits of any installed RAM board in each of the slots MEM0 through MEM3. The upper 29 bits are only valid on the register at 0x4d000, and contain additional information about the fault.

For the CM518B system board, the following table corresponds to the bits in Fault Register 2:

suhw31-26Upper halfword ECC syndrome bits
slhw25-20Lower halfword ECC syndrome bits
iobm19I/O Bus Master on Default
invadd18Invert low addr bit 2
decadd17Decrement low addr by 4
ioonly16I/O Bus Master on Fault
cpuio15CPU Accessing I/O Peripheral
bub014BuBUS Slot 0 master on fault
cpubub13CPU Accessing BuBUS Peripheral
bslav12-11BuBUS peripheral accessed by CPU
bub110BuBUS Slot 1 master on fault
bub29BuBUS Slot 2 master on fault
bub38BuBUS Slot 3 master on fault
reserved7-3Reserved (not used)
memeq2Memory equipped
memsz1-0Memory Size Array

Memory Size Information

As mentioned above, the memory equipped in each of the memory slots, MEM0 through MEM3, can be found in the lower three bits of each of the four Fault Register 2 locations. Memory must be installed sequentially! In other words, if there is no memory in slot MEM0, the system will not find any memory that may be installed in MEM1!

The lower two bits determine the size of memory installed in the slot, using a simple truth table:

Bit 1Bit 0Board SizeBytes
002 MB0x200000
018 MB0x800000
104 MB0x400000
1116 MB0x1000000

Control, Status, and Error Register Bit Assignments

BitDescriptionWrite AddressActiveHSPSPCSRCR
0Unix Interval Tier Timeout0x44000SETXX
1Power Down Request0x44004SETXXX
2Oper. Interrupt Level 150x44008SETXXX
3DUART Interrupt0x4400CSETXX
4DUART DMA Complete Interrupt0x44010SETXX
5PIR Level 90x44014SETXX
6PIR Level 80x44018SETXX
7Inhibit UNIX Interval Timer0x4401CSETXXX
8Inhibit System Sanity Timer0x44020SETXXX
9Inhibit UBUS Timer0x44024SETXXX
10Inhibit Faults to CPU0x44028SETXXX
11Inhibit Single Bit Error Rpt.0x4402CSETXX
12Inhibit Integral 3B2 I/O Bus0x44030SETXX
13Inhibit 4 BUB Slots0x44034SETXX
14Force ECC Syndrome0x44038CLEARXX
15Thermal Shutdown Request0x4403CSETXXX
16Failure LED ON0x44040SETXXX
17Power Down - Power Supply0x44044CLEARXX
18Floppy Speed Fast0x44048SETXX
19Floppy Side 10x4404CCLEARXX
20Floppy Motor On0x44050CLEARXXX
21Floppy Density0x44054SETXX
22Floppy Size0x44058SETXX
23Single Bit Error0x4405CSETXX
24Multiple Bit Error0x44060SETXX
25UBUS/BUB Received Fail0x44064SETXX
26UBUS Timer Timeout0x44068SETXX
27Fault Registers Frozen0x4406CSETXX
28Data Alignment Error0x44070SETXX
29Sanity Timer Timeout0x44074SETXX
30Abort Switch Activated0x44078SETXX
31System Reset Request0x4407CSETXX

SCSI Option Card (CM195W)



These ROMs contain the CIO code for the 80186.

NCR 8310

General Purpose 48mA Bus Transceiver, which provides single-chip open-collector interface to the SCSI bus.

NCR 5385E

SCSI Protocol Controller

AT&T 327CA

Some kind of PROM or PLA glue logic

MOSTEK MK4501N-12 (x4)

512 x 9 Parallel In-Out FIFO RAM

Harris CP82C37A

DMA Controller

Boot and Install Tape Format

System V Release 3.2.3 UNIX is available on a QIC-120 formatted, 120MB tape cartridge. The tape uses 512 byte blocks, with filemarks between files.

The standard layout of tapes is:

File NumberContents
1Essential Utilities cpio
2pkglist cpio
3 and on730KB floppy images containing packages listed in pkglist