MMU Caching Finally Explained

I had an absolute breakthrough tonight regarding how the WE32101 MMU handles caching. In fact, when I implemented the change, my simulator went from having 108 page miss errors during kernel boot, to 3. The cache is getting hit on almost every virtual address translation, and because of what I learned, the code is more efficient, too. The key to all this was finally looking up 2-way set associative caching Read More

3B2 System Timers and SIMH

I think I made a grievous error when I originally laid out how the 3B2 system timers would work in SIMH, and last night I started down the path of correcting that. The 3B2/400 has multiple sources of clocks and interrupts: There’s a programmable interval timer with three outputs being driven at 100KHz, a timer on the UART that runs at 235KHz, and a Time-of-Day clock. They’re all driven at Read More

Simulating the Disk Controller

I spent last night probing my 3B2/310’s hard disk controller with a logic analyzer so I can see exactly how it behaves, both with and without a hard disk attached to the system. It proved to be very tricky to get the logic analyzer probes attached because the motherboard is so incredibly dense. In fact, I couldn’t get a probe attached to the chip select line no matter how hard Read More

It’s Hard Disk Time

My next mini-project in the 3B2/400 simulator will be emulating the hard disk. The 3B2/400 used a NEC μPD7261A hard disk controller (PDF datasheet here), which has proved to be harder to emulate correctly than I would have liked. So far, my hard disk controller emulation has been limited to the most minimal functionality needed to get the emulator to pass self-checks at all. Other than that, it’s just a Read More

The Mystery of the Equipped Device Table

[EDIT: I have made a followup post detailing the answer to this mystery!] There is yet one more puzzling aspect of the 3B2 that I do not yet understand, and that is the equipped device table, or EDT. I’ve documented the nitty-gritty details on my main 3B2 reverse-engineering page, so I won’t bore you with the details. But the short version is this: The EDT is what tells the system Read More

A Last Word on MMU Caching

Over the weekend I conducted several experiments with caching using my 3B2 simulator. I learned a few critical bits of information. For background, see this post and this post. The first and most important thing I learned is that indexing cache entries only by their tags does not work. There are collisions galore, and no way to recover from them. However, if I index SD cache entries by the full Read More

MMU Caching Redux

I had a Eureka! moment last night about MMU caching, but it all came tumbling down this morning. My realization was that the Segment Descriptors are 8 bytes long, and that Page Descriptors are 4 bytes long. So, if we assume that the virtual address encodes the addresses of the SDs and PDs on word-aligned boundaries (and SDs and PDs are indeed word-aligned in memory), then you don’t need the Read More

MMU Caching for Fun and Profit

I’m in the middle of a very long, very drawn out project to try to emulate the AT&T 3B2/400 computer. I should probably have been sharing my progress more frequently than I have been, but it has for the most part been a painful and solitary endeavor. Today, though, there is something in particular that is bothering me greatly, and I must yell into the void to get this frustration Read More