Introduction and Overview

This document describes the internals of the AT&T 3B2 Revision 3 systems. These systems were released in the years following the release of the Revision 1 (AT&T 3B2/300) and Revision 2 (AT&T 3B2/310 and 3B2/400) systems, and represented an evolution of the architecture. There were numerous changes to firmware, memory map, and supported hardware.

Revision 3 systems included (but were not limited to):

• The 3B2/500
• The 3B2/600
• The 3B2/700
• The 3B2/800
• The 3B2/1000
• The 3B2/600G

Some of these names are merely marketing distinctions, while others represent different processor and MMU configurations. However, they all share the same basic system architecture.

This document focuses on the CM518B system board that was used in some models of 3B2/600, 3B2/700, and 3B2/1000.

Memory Map

The memory map of the Revision 3 systems is documented in the AT&T 3B2 Computer Technical Reference Manual on page 3-11 in section 3, Functional Description.

DMA Page Registers

These are 12-bit wide registers located at 0x45000, 0x46000, and 0x47000. They are write-only registers, and are used to set up the DMA page addresses for the integral floppy drive, UART A, and UART B, respectively. They are written as half-words, and are half-word aligned.

Floppy Control Register

The Floppy Control Register at address 0x40000 is an 8-bit register used to control which floppy drive is selected, and the amount of precompensation to use when writing.

Using this register, up to four floppy drives can be addressed by a single controller.

Fault Registers

There are two registers located at 0x4c000 and 0x4d000, respectively, called the fault registers. They are not documented in the the 3B2 Technical Reference Manual, but they are described somewhat more fully in the system header file /usr/include/sys/faultr.h.

The primary purpose is to hold information about system faults, but Fault Register 2 plays double duty. In addition to latching fault information, the bottom few bits of Fault Register 2 identify the type and number of RAM boards installed.

Fault Register 1

This 32-bit register holds the physical address of any fault in the its lower 26 bits.

Fault Register 2

This 32-bit register is a bit odd. There are actually four registers, addressed at 0x4d000, 0x4d004, 0x4d008, and 0x4d00c. The low three bits of each of these registers corresponds to the memory equipped and memory size bits of any installed RAM board in each of the slots MEM0 through MEM3. The upper 29 bits are only valid on the register at 0x4d000, and contain additional information about the fault.

For the CM518B system board, the following table corresponds to the bits in Fault Register 2:

Memory Size Information

As mentioned above, the memory equipped in each of the memory slots, MEM0 through MEM3, can be found in the lower three bits of each of the four Fault Register 2 locations. Memory must be installed sequentially! In other words, if there is no memory in slot MEM0, the system will not find any memory that may be installed in MEM1!

The lower two bits determine the size of memory installed in the slot, using a simple truth table:

Control, Status, and Error Register Bit Assignments

• PIR: Programmed Interrupt Request
• HS : Set by Hardware
• PS : Set by Programmed Control
• PC : Cleared by Programmed Control
• SR : Set by “System Reset” Signal
• CR : Cleared by “System Reset” Signal

SCSI Option Card (CM195W)

Components

ROM

These ROMs contain the CIO code for the 80186.

• ABLKK
• ABLKL

NCR 8310

General Purpose 48mA Bus Transceiver, which provides single-chip open-collector interface to the SCSI bus.

NCR 5385E

SCSI Protocol Controller

AT&T 327CA

Some kind of PROM or PLA glue logic

MOSTEK MK4501N-12 (x4)

512 x 9 Parallel In-Out FIFO RAM

Harris CP82C37A

DMA Controller

Boot and Install Tape Format

System V Release 3.2.3 UNIX is available on a QIC-120 formatted, 120MB tape cartridge. The tape uses 512 byte blocks, with filemarks between files.

The standard layout of tapes is: