AT&T 3B2 Revision 3 Internals

Introduction and Overview

This document describes the internals of the AT&T 3B2 Revision 3 systems. These systems were released in the years following the release of the Revision 1 (AT&T 3B2/300) and Revision 2 (AT&T 3B2/310 and 3B2/400) systems, and represented an evolution of the architecture. There were numerous changes to firmware, memory map, and supported hardware.

Revision 3 systems included (but were not limited to):

  • The 3B2/500
  • The 3B2/600
  • The 3B2/700
  • The 3B2/600G
  • The 3B2/800
  • The 3B2/1000

Some of these names are merely marketing distinctions, while others represent significant differences and capabilities. However, they all share the same basic system architecture.

This document focuses on the CM815B system board that was used in some models of 3B2/600, 3B2/700, and 3B2/1000.

Memory Map

The memory map of the Revision 3 systems is documented in the AT&T 3B2 Computer Technical Reference Manual on page 3-11 in section 3, Functional Description.

Address Description Width Size
0x00000000 Read-Only Memory [EPROM] 32 Bits 128 KB
0x00040000 Floppy Control Register 8 Bits 1 B
0x00041000 Timer -- --
0x00042000 NVRAM 8 Bits 2 KB
0x00044000 Control and Status Register (CSR) 32 Bits 4 B
0x00045000 Floppy DMA Page Register 12 Bits --
0x00046000 UARTA DMA Page Register 12 Bits --
0x00047000 UARTB DMA Page Register 12 Bits --
0x00048000 DMA Controller (9517) 8 Bits --
0x00049000 DUART (2681) 8 Bits 16 B
0x0004A000 Floppy Controller (1793) 8 Bits 2 B
0x0004B000 Reserved -- --
0x0004C000 Fault Register 1 32 Bits 1 W
0x0004D000 Fault Register 2 32 Bits 4 W
0x0004E000 Time of Day Clock 4 Bits --
0x0004F000 MMU (WE32106 or WE32206) -- --
0x00200000 Feature Card Slot 1 16 Bits 2 MB (Max)
0x00400000 Feature Card Slot 2 16 Bits 2 MB (Max)
0x00600000 Feature Card Slot 3 16 Bits 2 MB (Max)
0x00800000 Feature Card Slot 4 16 Bits 2 MB (Max)
0x00A00000 Feature Card Slot 5 16 Bits 2 MB (Max)
0x00C00000 Feature Card Slot 6 16 Bits 2 MB (Max)
0x00E00000 Feature Card Slot 7 16 Bits 2 MB (Max)
0x01000000 Feature Card Slot 8 16 Bits 2 MB (Max)
0x01200000 Feature Card Slot 9 16 Bits 2 MB (Max)
0x01400000 Feature Card Slot 10 16 Bits 2 MB (Max)
0x01600000 Feature Card Slot 11 16 Bits 2 MB (Max)
0x01800000 Feature Card Slot 12 16 Bits 2 MB (Max)
0x01A00000 Reserved 16 Bits 2 MB (Max)
0x01C00000 UBUS Connector 16 Bits 2 MB (Max)
0x02000000 Main Memory 32 Bits 64 MB
0x06000000 BUBUS Connector 1 16 Bits 64 MB
0x0A000000 BUBUS Connector 2 16 Bits 64 MB
0x0E000000 BUBUS Connector 3 16 Bits 64 MB
0x12000000 BUBUS Connector 4 16 Bits 64 MB
0xC0F00000 HW, SW Development System -- 1 MB
0xC1000000 Reserved for Diagnostics -- 1 MB

DMA Page Registers

These are 12-bit wide registers located at 0x45000, 0x46000, and 0x47000. They are write-only registers, and are used to set up the DMA page addresses for the integral floppy drive, UART A, and UART B, respectively. They are written as half-words, and are half-word aligned.

Register Address
Floppy 0x45002
UART A 0x46002
UART B 0x47002

Floppy Control Register

The Floppy Control Register at address 0x40000 is an 8-bit register used to control which floppy drive is selected, and the amount of precompensation to use when writing.

Using this register, up to four floppy drives can be addressed by a single controller.

Bit Function
0 Floppy Drive Select 0
1 Floppy Drive Select 1
2 Floppy Drive Select 2
3 Floppy Drive Select 3
4 Precompensation Bit 0
5 Precompensation Bit 1
6 Precompensation Bit 2
7 Force Precompensation

Fault Registers

There are two registers located at 0x4c000 and 0x4d000, respectively, called the fault registers. They are not documented in the the 3B2 Technical Reference Manual, but they are described somewhat more fully in the system header file /usr/include/sys/faultr.h.

The primary purpose is to hold information about system faults, but Fault Register 2 plays double duty. In addition to latching fault information, the bottom few bits of Fault Register 2 identify the type and number of RAM boards installed.

Fault Register 1

This 32-bit register holds the physical address of any fault in the its lower 26 bits.

Fault Register 2

This 32-bit register is a bit odd. There are actually four registers, addressed at 0x4d000, 0x4d004, 0x4d008, and 0x4d00c. The low three bits of each of these registers corresponds to the memory equipped and memory size bits of any installed RAM board in each of the slots MEM0 through MEM3. The upper 29 bits are only valid on the register at 0x4d000, and contain additional information about the fault.

For the CM518B system board, the following table corresponds to the bits in Fault Register 2:

Name Bits Purpose
suhw 31-26 Upper halfword ECC syndrome bits
slhw 25-20 Lower halfword ECC syndrome bits
iobm 19 I/O Bus Master on Default
invadd 18 Invert low addr bit 2
decadd 17 Decrement low addr by 4
ioonly 16 I/O Bus Master on Fault
cpuio 15 CPU Accessing I/O Peripheral
bub0 14 BuBUS Slot 0 master on fault
cpubub 13 CPU Accessing BuBUS Peripheral
bslav 12-11 BuBUS peripheral accessed by CPU
bub1 10 BuBUS Slot 1 master on fault
bub2 9 BuBUS Slot 2 master on fault
bub3 8 BuBUS Slot 3 master on fault
reserved 7-3 Reserved (not used)
memeq 2 Memory equipped
memsz 1-0 Memory Size Array
  • Memory Size Information

    As mentioned above, the memory equipped in each of the memory slots, MEM0 through MEM3, can be found in the lower three bits of each of the four Fault Register 2 locations. Memory must be installed sequentially! In other words, if there is no memory in slot MEM0, the system will not find any memory that may be installed in MEM1!

    The lower two bits determine the size of memory installed in the slot, using a simple truth table:

    Bit 1 Bit 0 Board Size Bytes
    0 0 2 MB 0x200000
    0 1 8 MB 0x800000
    1 0 4 MB 0x400000
    1 1 16 MB 0x1000000

Control, Status, and Error Register Bit Assignments

Bit Description Write Address Active HS PS PC SR CR
0 Unix Interval Tier Timeout 0x44000 SET X   X    
1 Power Down Request 0x44004 SET X X X    
2 Oper. Interrupt Level 15 0x44008 SET X X X    
3 DUART Interrupt 0x4400C SET X   X    
4 DUART DMA Complete Interrupt 0x44010 SET X   X    
5 PIR Level 9 0x44014 SET   X X    
6 PIR Level 8 0x44018 SET   X X    
7 Inhibit UNIX Interval Timer 0x4401C SET   X X X  
8 Inhibit System Sanity Timer 0x44020 SET   X X X  
9 Inhibit UBUS Timer 0x44024 SET   X X X  
10 Inhibit Faults to CPU 0x44028 SET   X X X  
11 Inhibit Single Bit Error Rpt. 0x4402C SET   X X    
12 Inhibit Integral 3B2 I/O Bus 0x44030 SET   X X    
13 Inhibit 4 BUB Slots 0x44034 SET   X X    
14 Force ECC Syndrome 0x44038 CLEAR   X X    
15 Thermal Shutdown Request 0x4403C SET X   X   X
16 Failure LED ON 0x44040 SET X X X    
17 Power Down - Power Supply 0x44044 CLEAR   X X    
18 Floppy Speed Fast 0x44048 SET   X X    
19 Floppy Side 1 0x4404C CLEAR   X X    
20 Floppy Motor On 0x44050 CLEAR   X X X  
21 Floppy Density 0x44054 SET   X X    
22 Floppy Size 0x44058 SET   X X    
23 Single Bit Error 0x4405C SET X   X    
24 Multiple Bit Error 0x44060 SET X   X    
25 UBUS/BUB Received Fail 0x44064 SET X   X    
26 UBUS Timer Timeout 0x44068 SET X   X    
27 Fault Registers Frozen 0x4406C SET X   X    
28 Data Alignment Error 0x44070 SET X   X    
29 Sanity Timer Timeout 0x44074 SET X   X    
30 Abort Switch Activated 0x44078 SET X   X    
31 System Reset Request 0x4407C SET   X     X
PIR
Programmed Interrupt Request
HS
Set by Hardware
PS
Set by Programmed Control
PC
Cleared by Programmed Control
SR
Set by "System Reset" Signal
CR
Cleared by "System Reset" Signal

SCSI Option Card (CM195W)

Components

ROM

These ROMs contain the CIO code for the 80186.

  • ABLKK
  • ABLKL

NCR 8310

General Purpose 48mA Bus Transceiver, which provides single-chip open-collector interface to the SCSI bus.

NCR 5385E

SCSI Protocol Controller

AT&T 327CA

Some kind of PROM or PLA glue logic

MOSTEK MK4501N-12 (x4)

512 x 9 Parallel In-Out FIFO RAM

Harris CP82C37A

DMA Controller